The right price for the DRAM would be more like $2.50 a piece in small quantity like 100, good luck for them selling the DRAM to someone.

Hank

Hi BFG,

Can you get the exact Part number of the RAM? -5 are 200MHz RAMs. I would be interested too, but 9$ a piece is expensive. I will try to get some -5 or -45, I have a little tinkerring in mind for my 6k.

The -54 replacement on my 6k board was not worth it, they would come up to 190s MHz range, just like the -6.

Hank

We still love to tinker with VooDoo!
Why?
Because we can

Depending on your skill level, you can learn a lot about 3D implementation. Sure you can read books etc., but you can not replace hands on experience and experimentation. Try that with some one elses hardware and software.

For those about to VooDoo, I salute you!

Hank

SDRAM replacement is not that hard for a skilled tech. I use a heat gun to remove the SDRAMs and then put them back on. Use enough flux and check your work closely (use a good SMT iron tip). I have done that on V5 6K with borrowed SDRAM from AAlchemy. When I did it, I made mistakes though, and had to take the card under microscope to find the solder bridge[:p]. I guess I am getting old and the eye site is going.

I do not know if that will buy you anything in speed improvement. Later on the -6 SDRAMs were marked down faster SDRAMs, since the memory vendor's wafers yielded faster then -6 on average. I have found the -6 memory will oveclock as easily as -55 and -54.

I would rate the job as 5, medium difficulty.

Hank

Last week I had lunch with the rest of the systems engineering from 3DFX, the Evil TRIO of engineers. Nice feeling, we loved to bring stuff to you, which was ahead of it's time and little bit evil. There would have been more, but the bean counters decided to bail.

Anyway, board like this is a proof that people appreciated what we have done . hehe

Hank[}:)]

I have checked with ABIT, they have done on board VGA disable only on AGP card insert, and did not provide VGA boot order in BIOS. Very sloppy of them.

You are right, V5 BIOS must complete some initialization, because it is missing from the driver. We had to do a patch in one situation to partialy boot a VGA device and return control to on board VGA, to get the device stable. There is no way you can do that by yourself.

The only way to fix this is for ABIT to add the 2 missing BIOS features back in.

Hank

I read through the whole discussion, but not once you have mentioned the manufacturer and model of the mother board!! Kinda hard to help with the problem,

Hank

If I remember right, but this is from looooong time ago, I have disabled the on board VGA in the Device Manager. Open display adapters, right click on the undesired VGA adapter and disable.

Hank

Rampage is a code name for the chip. Habanero was it's predecessor (RAMPY with 256 bit DDR memory bus).

SAGE is a code name for the chip (lead engineer "Captain Inverter")

SPECTER is a code name for the board (SPecial Executive for Control, Terrorism, Extortion, and Revenge.) Name was picked by the boards designer "Brian a.k.a. Crap With Legs"

Hank a.k.a. FUBAR or Crap with Hands

SPECTER was an internal name. If you remember James Bond, the you know what it stands for

Offical Product name was not assigned to Rampage boards.

Hank

Hi,

Looking at the back of the card, I can see the strapping resistors were changed for card stability at 4x FSAA. It should run fine. You can always take a snaphot from behind the Hint bridge so I can be sure.

I am still running mine on KT266 based chipsets. Congrats on the nice card

Hank

The card is OK, has all the mods applied.

Tested at 4 FSAA and stable.

Good Thing!!!

The card was modded and tested (burned in) by me for a friend.

Have fun

Dual AAlchemy board renders to 1 monitor. They are in 16 chip SLI. The boards are linked together.

Hank

Well a little more on the bug.

everytime I run the Q3ADEMO, FIFO hole counter reports that 4 DWORDS are missing to close the hole.

Magically Hint bridge has 4DWORD Delayed Transaction FIFO. It is possible that the system discards the writes, and locks the system.

I'll try to get rev CC Hint Bridge and see if an undocumented feature slipped into rev B Hint chips . The only way to get arround this is to implement Hole Counter interrupt from 6k and recopy the fifo contents to avoid a lock.

That means that the driver would have to keep a local copy of fifo contents, not a long one, and do a move to VSA100 fifo. With PIII it mght be a small performance penalty.

Hank